1. Field of the Invention
The present invention relates to field-effect transistor (FET) integrated circuits. In particular, the present invention relates to control of threshold voltage of FETs of an integrated circuit.
2. Description of the Prior Art
In integrated circuits which utilize FETs, it is important to achieve precise control of the threshold voltage of FETs forming the integrated circuit. Although significant advantages have been made by close control of device fabrication parameters, in many applications unavoidable variations in device fabrication parameters prevent the desired degree of control of threshold voltage.
In the past, threshold control circuits have been proposed which have used oscillators to provide charge pumping to the substrate of FET integrated circuits. U.S. Pat. Nos. 4,115,710 by Lou; 4,229,667 by Heimbigner et al; and 4,142,114 by Green show examples of this type of threshold control circuit.
Another problem which has been encountered in the fabrication of integrated circuit enhancement mode FETs is that in some fabrication processes a special threshold adjustment ion implantation step is not used because it is incompatible with the remainder of the device fabrication process. In these cases, there is a tendency of the resulting FETs to be weak depletion mode devices (with a threshold voltage on the order of -0.1 volt), rather than enhancement mode devices. For low power applications, enhancement mode devices are desired because they are normally "off" devices. Those FETs which turn out to be depletion mode devices are unsuitable, thus reducing yields.
FET integrated circuits have found wide application as semiconductor digital memories. For high speed reading and writing of data in the semiconductor memory, relatively high currents are required. These same current levels are not required, however, during standby conditions. One increasingly important requirement for semiconductor memories is low standby power drain, which necessarily means that low currents be used to maintain memory contents during standby. One technique for reducing circuit standby power is described in J. M. Caywood, et al, "A Novel 4K Static RAM with Submilliwatt Standby Power", IEEE Transactions on Electron Devices, Vol. ED-26, pages 861-864 (June 1979). In FIG. 6 of this article, a chip enable (CE) buffer circuit is illustrated which switches the memory from a "power down" state to a "power up" state upon application of a chip enable (CE) signal. The buffer circuit relies on charging a capacitor, which in turn transfers charge to gates internal to the memory circuit in order to switch the circuit from a power down to a power up state.